library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity fsm is
port(
clk : in std_logic;
rstn : in std_logic
);
end entity;
architecture rtl of fsm is
type state_type is (S0, S1);
type reg_type is record
state : state_type;
end record;
signal r, rin : reg_type;
begin
comb: process(r)
variable v : reg_type;
begin
v := r;
case r.state is
when S0 =>
v.state := S1;
when S1 =>
v.state := S0;
end case;
rin <= v;
end process;
reg: process(clk)
begin
if rising_edge(clk) then
if rstn='0' then
r <= (state => S0);
else
r <= rin;
end if;
end if;
end process;
end rtl;